1 | /* |
2 | * rtGetInf.cpp |
3 | * |
4 | * Academic License - for use in teaching, academic research, and meeting |
5 | * course requirements at degree granting institutions only. Not for |
6 | * government, commercial, or other organizational use. |
7 | * |
8 | * Code generation for model "Arduino_skal". |
9 | * |
10 | * Model version : 1.1 |
11 | * Simulink Coder version : 9.5 (R2021a) 14-Nov-2020 |
12 | * C++ source code generated on : Thu Apr 15 15:56:50 2021 |
13 | * |
14 | * Target selection: grt.tlc |
15 | * Note: GRT includes extra infrastructure and instrumentation for prototyping |
16 | * Embedded hardware selection: Intel->x86-64 (Windows64) |
17 | * Code generation objective: Debugging |
18 | * Validation result: Not run |
19 | */ |
20 | |
21 | /* |
22 | * Abstract: |
23 | * Function to initialize non-finite, Inf |
24 | */ |
25 | #include "rtGetInf.h" |
26 | #define NumBitsPerChar 8U |
27 | |
28 | extern "C" { |
29 | /* |
30 | * Initialize rtInf needed by the generated code. |
31 | * Inf is initialized as non-signaling. Assumes IEEE. |
32 | */ |
33 | real_T rtGetInf(void) |
34 | { |
35 | size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar); |
36 | real_T inf = 0.0; |
37 | if (bitsPerReal == 32U) { |
38 | inf = rtGetInfF(); |
39 | } else { |
40 | uint16_T one = 1U; |
41 | enum { |
42 | LittleEndian, |
43 | BigEndian |
44 | } machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian; |
45 | switch (machByteOrder) { |
46 | case LittleEndian: |
47 | { |
48 | union { |
49 | LittleEndianIEEEDouble bitVal; |
50 | real_T fltVal; |
51 | } tmpVal; |
52 | |
53 | tmpVal.bitVal.words.wordH = 0x7FF00000U; |
54 | tmpVal.bitVal.words.wordL = 0x00000000U; |
55 | inf = tmpVal.fltVal; |
56 | break; |
57 | } |
58 | |
59 | case BigEndian: |
60 | { |
61 | union { |
62 | BigEndianIEEEDouble bitVal; |
63 | real_T fltVal; |
64 | } tmpVal; |
65 | |
66 | tmpVal.bitVal.words.wordH = 0x7FF00000U; |
67 | tmpVal.bitVal.words.wordL = 0x00000000U; |
68 | inf = tmpVal.fltVal; |
69 | break; |
70 | } |
71 | } |
72 | } |
73 | |
74 | return inf; |
75 | } |
76 | |
77 | /* |
78 | * Initialize rtInfF needed by the generated code. |
79 | * Inf is initialized as non-signaling. Assumes IEEE. |
80 | */ |
81 | real32_T rtGetInfF(void) |
82 | { |
83 | IEEESingle infF; |
84 | infF.wordL.wordLuint = 0x7F800000U; |
85 | return infF.wordL.wordLreal; |
86 | } |
87 | |
88 | /* |
89 | * Initialize rtMinusInf needed by the generated code. |
90 | * Inf is initialized as non-signaling. Assumes IEEE. |
91 | */ |
92 | real_T rtGetMinusInf(void) |
93 | { |
94 | size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar); |
95 | real_T minf = 0.0; |
96 | if (bitsPerReal == 32U) { |
97 | minf = rtGetMinusInfF(); |
98 | } else { |
99 | uint16_T one = 1U; |
100 | enum { |
101 | LittleEndian, |
102 | BigEndian |
103 | } machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian; |
104 | switch (machByteOrder) { |
105 | case LittleEndian: |
106 | { |
107 | union { |
108 | LittleEndianIEEEDouble bitVal; |
109 | real_T fltVal; |
110 | } tmpVal; |
111 | |
112 | tmpVal.bitVal.words.wordH = 0xFFF00000U; |
113 | tmpVal.bitVal.words.wordL = 0x00000000U; |
114 | minf = tmpVal.fltVal; |
115 | break; |
116 | } |
117 | |
118 | case BigEndian: |
119 | { |
120 | union { |
121 | BigEndianIEEEDouble bitVal; |
122 | real_T fltVal; |
123 | } tmpVal; |
124 | |
125 | tmpVal.bitVal.words.wordH = 0xFFF00000U; |
126 | tmpVal.bitVal.words.wordL = 0x00000000U; |
127 | minf = tmpVal.fltVal; |
128 | break; |
129 | } |
130 | } |
131 | } |
132 | |
133 | return minf; |
134 | } |
135 | |
136 | /* |
137 | * Initialize rtMinusInfF needed by the generated code. |
138 | * Inf is initialized as non-signaling. Assumes IEEE. |
139 | */ |
140 | real32_T rtGetMinusInfF(void) |
141 | { |
142 | IEEESingle minfF; |
143 | minfF.wordL.wordLuint = 0xFF800000U; |
144 | return minfF.wordL.wordLreal; |
145 | } |
146 | } |
147 |